The invention is related to the field of semiconductor devices and more particularly to substantially linear semiconductor capacitors produced with a fabrication process primarily designed for CMOS logic.
Mixed signal devices utilizing both analog and digital circuits frequently require linear capacitors for use in the analog circuitry. Typically, the integration of a process suitable for manufacturing these capacitors with an otherwise conventional, digital CMOS fabrication process has introduced additional cost and/or complexity into the fabrication process or has resulted in capacitors that lack the desired linearity over a sufficient range of biasing conditions. As an example, linear capacitors have been fabricated using two polysilicon deposition steps (double poly processes) in which polysilicon comprises both plates of the capacitor. While double poly processes are capable of producing adequate capacitors, most baseline CMOS fabrication processes must be modified to produce the second poly structure needed for the capacitor. The addition of this second poly structure and the corresponding deposition, mask, and etch steps required undesirably add cost, complexity, and cycle time to the corresponding process. Metal/metal capacitors, in which a pair of deposited metal layer separated by an interlevel dielectric form the capacitor, have also been investigated. In one example, the metal/metal capacitor is fully integrated into the backend of an existing fabrication process such that the existing metal and oxide deposition steps are used to produce the capacitor. Unfortunately, the use of existing metal structures in conjunction with the thick interlevel dielectrics characteristic of contemporary fabrication processes results in large area and typically imprecise capacitors. Moreover, while it would be desirable to utilize a high permittivity dielectric for the capacitor to obtain the greatest capacitance possible for a given capacitor plate area, the trend in the industry is to utilize low permittivity dielectrics for interlevel dielectrics to reduce coupling between successive metal layers. Other metal/metal capacitors have been proposed using tantalum (Ta) or tantalum nitride (TaN) plates, but Ta or TaN capacitors introduce multiple additional deposition and masking steps that increase the cost of the process. Therefore, it is highly desirable to implement a semiconductor process suitable for fabricating reliable and linear capacitors that can be integrated into an existing or baseline CMOS fabrication process without adding cost in the form of additional processing.